Diploma in VLSI-Design

(2000 – 01)

C-DAC

(Govt of India Undertaking)

Certified

B.E. – Electronics and Power

(1996 – 2000)

Nagpur University

59%

Senior Secondary School – 12^th Grade    (1995 – 96)

I.C.S.E.

73%

Higher Secondary School – 10^th Grade    (1993 – 94)

I.S.C

72%

Associated Electronics Research Foundation, New Delhi.

Trainee Engineer

2003 (4 months)

May-Aug

1) Generic Wrapper architecture and Wrapper architectural refinement of Internal Bus using quasi-static scheduling approach for optimal IB (Internal Bus) usage for multi core SOC. Design (RTL) and testing of Auto-Baud rate controller / converter with clock 49.152 MHz, clock factor 8 with supporting baud rates of 300-115200.

Language: VHDL

Tool used: FPGA Ex.II 3.3.0v, MAX PLUS 2 10.1, Xilinx Alliance Series (Xilinx)

2) Study on D.S.P computational units (Mathematical modeling of Circuits and    

      Filters).

Bharat Electronics Limited (B.E.L) Ministry of Defence undertaking, Sahibabad.

Graduate Apprentice

Sep 2003 – Dec 2003

Worked as Graduate Apprentice in Microwave Components Division.

C-DAC

MAIN PROJECT:

Design of BlueTooth Baseband Controller:

Design and testing of the hardware layer termed as Baseband Link Controller of BLUETOOTH (IP) technology, targeted on Virtex II (Xilinx). Basic functions implemented were:  

a)  Different error correction scheme for different types of   

Packets.

      b) Packet Handling.

 c) Synchronization of the clocks and their connection

     establishment.

      d) Frequency hop selection.

      e) Generation of Data packets.

Project consisted of designing various types of data packets according to their functions. Clock synchronization issues and their error checking schemes both on transmitter and receiver side of the device. Design was coded using behavioral and RTL coding style .

Language: VHDL

Tool used: Model-Sim 5.5e, Leonardo-Spectrum 2000_1a, Xilinx Alliance Series (Xilinx)

Flow: Script based

MINI PROJECT

Ethernet MAC Transmitter (Cyclic Redundancy Check Generator).

         Number of Team members: 3

         Duration  - 3 days

Description:   In Ethernet Transmitter it basically checks the error in the data of the transmitter with the help of control signals from Frame Assembler. Design was purely digital based on the RTL coding style.

B.E

(Final Year)

Final year project deals with the study of U.P.F.C (Unified Power Flow Controller) FACT (Flexible AC Transmission) block designing using solid state back-to-back inverter connection to improve power angle/ power factor at the destination sub-station and to reduce reactive power effects using SSSC compensation. 

CDAC

Critical path analysis and issues during ASIC design. 

BLUETOOTH technology and feasibility.

Power Amplifier

Logic Synthesis

Simulator

Model Sim 5.5e, MAX-PLUS II

Synthesis

Leonardo Spectrum 2000_1a_OEM

FPGA Ex.II 3.3.0v

P & R

(Automated) XDM (xilinx), MAX-PLUS II 10.1.

Technology (FPGA)

Virtex II (Xilinx), Flex 10k(Altera)

Layout designing

MAGIC (Berkley version)

Programming language (h/w)

VHDL, Verilog.

Programming language (s/w)

C, C++.